GENCTRL[2]

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Interpret as GENCTRL[2]

SRC=XOSC

Generic Clock Generator Control

SRC	Source Select 0 (XOSC): XOSC oscillator output 1 (GCLKIN): Generator input pad 2 (GCLKGEN1): Generic clock generator 1 output 3 (OSCULP32K): OSCULP32K oscillator output 4 (XOSC32K): XOSC32K oscillator output 5 (OSC16M): OSC16M oscillator output 6 (DFLLULP): DFLLULP output 7 (FDPLL96M): FDPLL output
GENEN	Generic Clock Generator Enable
IDC	Improve Duty Cycle
OOV	Output Off Value
OE	Output Enable
DIVSEL	Divide Selection
RUNSTDBY	Run in Standby
DIV	Division Factor

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